1. Field of the Invention
Embodiments of the present invention are related to semiconductor memory devices. In particular, embodiments of the invention are related to flash memory devices.
This application claims priority to Korean Patent Application No. 2005-80164, filed Aug. 30, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
Flash memory is one type of non-volatile memory. It is commonly used as a replacement for conventional electrically erasable programmable read only memory (EEPROM) which is generally formed by plural memory sectors, each being erasable and/or programmable using a single programming operation. Thus, while conventional EEPROM devices are well adapted to slow speed applications which do not suffer from the fact that erase and programming operations must be carried on a memory block by memory block basis, flash memory devices are efficiently adapted to higher speed applications (e.g., applications running at higher clock frequencies), since a system employing flash memory may read and write data to separate memory blocks at the same time.
However, both flash memory devices and EPROM devices have a limited lifetime due to the presences of certain insulation films that break down with use over time. These insulation films are generally associated with storage elements and are gradually destroyed by the hundreds and thousands of erase and programming operations performed on the respective memory devices.
Like all non-volatile memory devices, flash memory devices store information even when power is not applied to the device. Thus, information stored in the device is retained during power interruptions. Flash memory devices are also very resistant to physical shocks and provide a fast access time during read operations. Owing to such merits, flash memory devices are commonly employed within the memory system of host devices powered by a battery.
Flash memory devices may be classified into NOR and NAND type devices, in accordance with the primary type of logic gate used in their architecture. The memory cells of a flash memory device are formed in an array, and each cell in the array is typically adapted to store a single bit of information. However, multi-level cells are designed to store more than one bit of information by varying the amount of electrical charge accumulated on a constituent floating gate.
In a NOR flash memory device, each memory cell is very similar in structure to that of a typical MOSFET transistor, except that it has two gates. One gate is called the control gate (CG) and it generally operates like the gate of an MOS transistor. The other gate is called a floating gate (FG) and is electrically isolated by a surrounding insulation film. The floating gate is interposed between the control gate and the substrate (or a bulk material).
Since the floating gate is electrically isolated by the insulation film, electrons near the floating gate tend to accumulate on the floating gate and may be variously used to store information. Electrons accumulating on the floating gate influence an electric field associated with the control gate (e.g., partially offsetting the electric field) and thereby change the threshold voltage of the memory cell. Thus, in response to a specific voltage applied to the control gate during a read operation, current may or may not flow through the memory cell in accordance with its threshold voltage. Such current flow is regulated by the amount of charge accumulated on the floating gate. A data value of “1” or “0” is detected in accordance with whether or not current flows, where the current flow corresponds to data stored in the memory cell. However, in the multi-level cell storing more than one bit per cell, an accumulation of electrons on a floating gate may be detected in accordance with a corresponding amount of current flowing through the memory cell, rather than the mere presence or absence of current.
A NOR flash memory cell is typically programmed (i.e., a data value is stored) by applying a program voltage to the control gate, applying a high voltage (e.g., about 5 to 6V) to the drain. Under this bias condition, a relatively large current flows from drain to source. This type of programming scheme is referred to as “hot electron injection.” During an erase operation for the NOR flash memory cell, a high voltage gap is established between the control gate and substrate (or bulk material), which induces a so-called Fowler-Nordheim tunneling effect to release the electrons accumulated on the floating gate.
A cell array of NOR flash memory devices is usually divided into blocks or sectors that are erased as a unit. Memory cells belonging to a particular block are erased at the same time during a single erase operation. Otherwise, a programming operation for the NOR flash memory device may be carried out on a byte or word basis.
Erase operations for a NOR flash memory device may include a pre-program operation, a main erase operation, and a post-program operation. The pre-program operation is performed using bias conditions similar to those of the programming operation. These conditions prevent memory cells from being over-erased into depletion during a subsequent main erase operation. All memory cells in a sector to be erased may be pre-programmed. Next, a main erase operation may be performed such that all memory cells in the sector are placed in an “ON” state. Finally, a post-program operation may be performed to correct any over-erased memory cells. Except for its particular bias conditions, a post-program operation may be performed in a manner similar to that of a pre-program operation.
As noted above, since the erase operations applied to a NOR flash memory device generally include several different operations, the speed of the erase operation is slower than a read operation. This reality is further complicated by the fact that as the operational voltage of the memory device is reduced, the gate voltage for the MOS transistor is also reduced, and the current capacity of the MOS transistor drops. As current capacity drops, it takes longer and longer to charge and discharge the various voltages used during an erase operation. This means that the speed of the erase operation for a NOR flash memory device is effectively decreased as its operating voltage is decreased.